▎ 摘　　要

This study investigated on the effects of gate dielectrics for field effect transistors (FETs). The gate dielectrics with organic and inorganic layers were deposited on Si (100) substrates using cyclohexane and tetraethyl orthosilicate (TEOS) by plasma enhanced chemical vapor deposition (PECVD) method. After the Si (100) substrates were dry-cleaned by in situ Ar plasma bombardment with 60 W for 15 min., the gate dielectric plasma polymer thin films deposited under plasma power between 20 W and 60 W with different precursor flow ratio. Also, the active graphene layer was grown on a Ni substrate using CH4 by low-pressure thermal chemical vapor deposition (CVD) method, and the Ni substrate was then etched away. In order to fabricate a back-gate graphene-based FET, the graphene layer was adsorbed onto the plasma-polymer gate dielectric film, then 80 nm thick Au electrodes were finally evaporated onto the graphene using a mask with a gap of 370 nm, and a probe-station system was utilized to characterize the devices. As the plasma power and flow rate of TEOS increases, the gate voltage moves at a positive voltage, indicting p-doping by high fragmented Si and O elements under high plasma power and TEOS flow rate.