▎ 摘　　要

We present a novel method for fabricating large-area field-effect transistors (FETs) based on densely packed multichannel graphene nanoribbon (GNR) arrays using advanced direct self-assembly (DSA) nanolithography. The design of our strategy focused On the efficient integration of the FET channel and using fab-compatible processes such as thermal annealing and chemical vapor deposition. We achieved linearly stacked DSA nanopattern arrays with sub-10 nm half pitch critical dimensions (CD) by controlling the thickness of topographic Au confinement patterns. Excellent roughness values (similar to 10% of CD) were obtained, demonstrating the feasibility of integrating sub-10 nm GNRs into commercial semiconductor processes. Based on this facile process, FETs with such densely packed multichannel GNR arrays were successfully fabricated on 6 in. silicon wafers. With these high-quality GNR arrays, we achieved FETs showing the highest performance reported to date (an on-to-off ratio larger than 10(2)) for similar devices produced using conventional photolithography and block-copolymer lithography.