▎ 摘　　要

We have fabricated at wafer level field-effect-transistors (FETs) having as channel graphene monolayers transferred on a HfZrO ferroelectric, grown by atomic layer deposition on a doped Si (100) substrate. These FETs display either horizontal or vertical carrier transport behavior, depending on the applied gate polarity. In one polarity, the FETs behave as a graphene FET where the transport is horizontal between two contacts (drain and grounded source) and is modulated by a back-gate. Changing the polarity, the transport is vertical between the drain and the back-gate and, irrespective of the metallic contact type, Ti/Au or Cr/Au, the source-drain bias modulates the height of the potential barrier between HfZrO and the doped Si substrate, the carrier transport being described by a Schottky mechanism at high gate voltages and by a space-charge limited mechanism at low gate voltages. Vertical transport is required by three-dimensional integration technologies to increase the density of transistors on chip.