▎ 摘　　要

The potential performance of 2D NAND flash with a graphene floating gate (FG) layer is presented. The field enhancement factor for patterned CVD graphene sheets atop a tunneling dielectric is experimentally extracted and used to drive higher-level circuit simulations on 64-bit NAND strings. The average field enhancement factor at a barrier height of 3.1 eV was found to be similar to 2.85 with a maximum value of 4. Our modest extracted beta value explains the contradiction in prior experiments that reported a field enhancement factor of few thousands but only 30%-40% improvement in the write voltage of FG memory devices. Design and operational tradeoffs are benchmarked based on these experimental values and it is shown that 2D NAND programming time and/or programming voltage can be suppressed to 10 ns and 5 V, respectively, based on a 65 nm process node. The onset of read disturbs from the more efficient FG layer are identified and shown to be easily mitigated through error correction code.