▎ 摘　　要

McCulloch-Pitts neuron structures are comprised of a number of synaptic inputs and a decision element, called soma. In this paper, we propose a 5-bit Graphene Nanoribbon (GNR)-based DAC to fulfill the role of the summation element featuring programmable input weights. The proposed GNR-based 5-bit DAC relies on: (i) GNR unit current cells and (ii) a GNR logic thermometric decoding block. Our implementation is based on mapping the GNR structure's conductance using Matlab and performing the required SPICE analysis using the Matlab based GNR Verilog-A model. The unit current cell geometry and bias conditions were chosen based on the unit cell's conductance map from which we derived its $I_{ON}$/$I_{OFF}$ ratio, as well as transfer and output characteristics, resembling the classical MOSFET counterpart. By utilizing GNR devices instead of FinFET counterparts, a reduction of the active area of the 5-bit current DAC by up to a factor of three can be achieved. Furthermore, the GNR implementation achieved this while maintaining comparable INL and DNL performance to that of the FinFET variant, i.e., DNL of [-0.196, 0.088] LSB and INL of [-0.809, 0.364] LSB for the proposed GNR 5-bit DAC while operating at a supply voltage of only 0.2 V.