▎ 摘　　要

The synthesis of graphene on cubic silicon carbide on silicon pseudosubstrates draws enormous interest due to the potential integration of the 2D material with the well-established silicon technology and processing. However, the control of transport properties over large scales on this platform, essential for integrated electronics and photonics applications, has lagged behind so far, due to limitations such as 3C-SiC/Si interface instability and nonuniform graphene coverage. We address these issues by obtaining an epitaxial graphene (EG) onto 3C-SiC on a highly resistive silicon substrate using an alloy-mediated, solidsource graphene synthesis. We report the transport properties of EG grown over large areas directly on 3C-SiC(100) and 3C-SiC(111) substrates, and we present the corresponding physical models. We observe that the carrier transport of EG/3C-SiC is dominated by the graphene-substrate interaction rather than the EG grain size, sharing the same conductivity and same inverse power law as EG on 4H- or 6H-SiC(0001) substrates- although the grain sizes for the latter are vastly different. In addition, we show that the induced oxidation/silicates at the EG/3C-SiC interface generate a p-type charge in this graphene, particularly high for the EG/3C-SiC(001). When silicates are at the interface, the presence of a buffer layer in the EG/3C-SiC(111) system is found to reduce somewhat the charge transfer. This work also indicates that a renewed focus on the understanding and engineering of the EG interfaces could very well enable the long sought-after graphene-based electronics and photonics integrated on silicon.