▎ 摘　　要

We investigate the device operation and performance of transistors based on a graphene nanomesh lattice. By means of numerical simulation, we show that this device architecture allows suppressing the chiral tunneling, which reduces drastically the off current and enhances the on/off ratio compared to the pristine graphene counterpart. Additionally, a good saturation of current can be reached in the thermionic regime of transport. Though reduced compared to the case of pristine transistors, the transconductance and the cutoff frequency are still high. Above all, the nanomesh transistors outperform their pristine graphene counterpart in terms of voltage gain and maximum oscillation frequency. (C) 2013 AIP Publishing LLC.