• 文献标题:   Low Operating Bias and Matched Input-Output Characteristics in Graphene Logic Inverters
  • 文献类型:   Article
  • 作  者:   LI SL, MIYAZAKI H, KUMATANI A, KANDA A, TSUKAGOSHI K
  • 作者关键词:   graphene, alumina dielectric, logic gate, inverter, nanoelectronic
  • 出版物名称:   NANO LETTERS
  • ISSN:   1530-6984
  • 通讯作者地址:   Natl Inst Mat Sci
  • 被引频次:   78
  • DOI:   10.1021/nl100031x
  • 出版年:   2010

▎ 摘  要

We developed a simple and novel method to fabricate complementary-like logic inverters based on ambipolar graphene held-effect transistors (FETs) We found that the top gate stacks (with both the metal and oxide layers) can be simply prepared with only one-step deposition process and show high capacitive efficiency By employing such a top gate as the operating terminal, the operating bias can be lowered within 2 V In addition, the complementary p- and n-type FET pairs can be also simply fulfilled through potential superposition effect from the drain bias The inverters can be operated. with up to 4-7 voltage gains, in both the first and third quadrants due to the ambipolarity of graphene FETs For the first time, a match between the input and output voltages is achieved in graphene logic devices, indicating the potential in direct cascading of multiple devices for future nanoelectronic applications