▎ 摘　　要

In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance (g(ds)), transconductance (g(m)), gate to drain capacitance (C-gd) and gate to source capacitance (C-gs) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than 16% NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.