▎ 摘　　要

Polymer ferroelectric-gate field effect transistors (Fe-FETs) employing ferroelectric polymer thin films as gate insulators are highly attractive as a next-generation non-volatile memory. For minimizing gate leakage current of a device which arises from electrically defective ferroelectric polymer layer in particular at low operation voltage, the materials design of interlayers between the ferroelectric insulator and gate electrode is essential. Here, we introduce a new solution-processed interlayer of conductive reduced graphene oxides (rGOs) modified with a conjugated block copolymer, poly(styrene-block-paraphenylene) (PS-b-PPP). A FeFET with a solution-processed p-type oligomeric semiconducting channel and ferroelectric poly(vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) insulator exhibited characteristic source-drain current hysteresis arising from ferroelectric polarization switching of a PVDF-TrFE insulator. Our PS-b-PPP modified rGOs (PMrGOs) with conductive moieties embedded in insulating polymer matrix not only significantly reduced the gate leakage current but also efficiently lowered operation voltage of the device. In consequence, the device showed large memory gate voltage window and high ON/OFF source-drain current ratio with excellent data retention and read/write cycle endurance. Furthermore, our PMrGOs interlayers were successfully employed to FeFETs fabricated on mechanically flexible substrates with promising non-volatile memory performance under repetitive bending deformation. (C) 2014 Elsevier B.V. All rights reserved.