▎ 摘　　要

Electrostatically doped graphene p-n junctions can be formed by applying large source-drain and source-gate biases to a graphene field-effect transistor, which results in trapped charges in part of the channel gate oxide. We measure the temperature distribution in situ during the electrical stress and characterize the resulting p-n junctions by Raman spectroscopy and photocurrent microscopy. Doping levels, the size of the doped graphene segments, and the abruptness of the p-n Junctions are all extracted. Additional voltage probes can limit the length of the doped segments by acting as heat sinks. The spatial location of the identified potential steps coincides with the position where a photocurrent is generated, confirming the creation of p-n junctions.