• 文献标题:   Demonstration of a Subthreshold FPGA Using Monolithically Integrated Graphene Interconnects
  • 文献类型:   Article
  • 作  者:   LEE KJ, PARK H, KONG J, CHANDRAKASAN AP
  • 作者关键词:   cmos integrated circuit, graphene, interconnect
  • 出版物名称:   IEEE TRANSACTIONS ON ELECTRON DEVICES
  • ISSN:   0018-9383 EI 1557-9646
  • 通讯作者地址:   Samsung Elect Co Ltd
  • 被引频次:   13
  • DOI:   10.1109/TED.2012.2225150
  • 出版年:   2013

▎ 摘  要

We have demonstrated a subthreshold FPGA system using monolithically integrated graphene wires. The graphene wires replace double-length lines in the interconnect fabric of a custom FPGA implemented in 0.18-mu m CMOS. The four-layer graphene wires have lower capacitance than the CMOS aluminum wires, resulting in up to 2.11x faster speeds and 1.54x lower interconnect energy when driven by a low-swing voltage of 0.4 V. This paper presents the first graphene-based system application and experimentally demonstrates the potential of using low-capacitance graphene wires for ultralow power electronics.