▎ 摘　　要

A new strategy for the integration of graphene electronics with silicon complementary metal-oxide-semiconductor (Si-CMOS) technology is demonstrated that requires neither graphene transfer nor patterning. Inspired by silicon-on-insulator and three-dimensional device hyper-integration techniques, a thin monocrystalline silicon layer ready for CMOS processing is bonded to epitaxial graphene (EG) on SiC. The parallel Si and graphene electronic platforms are interconnected by metal vias. In this method, EG is grown prior to bonding so that the process is compatible with EG high temperature growth and preserves graphene integrity and nano-structuring.