▎ 摘　　要

In recent years, efforts to perform more processing operation on a silicon chip have made a strong enthusiasm for making the circuit components smaller in order to reduce the power and increase the speed. Due to silicon constraints, there will be no possibility to follow Moore's law. That's why we should look for an alternative to silicon. Therefore, due to high mobility, high current density, and low noise, the study on Graphene Nano Ribbon (GNR) began. ADCs and DACs have a major share in the electronics industry. An ADC prepares signals for the digital world and microprocessor processing. There are different methods for converting analog to digital signals. Among them, due to unique features such as high speed; Flash ADC has attracted the attention of designers. In this research first, a model for simulating of the GNR field effect transistor (GNRFET), is introduced. Then, this model is used to design a flash ADC. The results of this study indicate that the designed circuit has a desirable performance as an ADC. In addition, compared to a same Si-CMOS sample, errors such as DNL, INL, Offset, and Full scale are reduced. Moreover, GNR-based ADC shows less power consumption. The maximum and minimum power consumption are equal to 27.8% and 17.6% which corresponds to 5-bit and 4-bit GNR-based flash ADCs compared with their CMOS counterpart. Moreover, this research indicates a significant improvement in the delay that is at least 86.3% and maximum 88.6% which corresponds to 5-bit and 3-bit GNR-based flash ADCs. (c) 2019 The Electrochemical Society.