▎ 摘　　要

A quantitative model is developed to explain the antihysteretic behavior of the electrical resistivity of graphene on a ferroelectric Pb(Zr (x) Ti1 - x )O-3 substrate as a function of the gate voltage. The model takes into account the trapping of the electrons from the graphene layer by the states related to the graphene-ferroelectric interface. The finite energy gap of impurity states is also taken into account, which makes it possible to describe the well-known experimental dependences, including an increase and the subsequent saturation of a "memory window" with the switching gate voltage. The obtained estimates can be important for creating next-generation nonvolatile memory elements, which use the two stable values of electrical resistivity (one of them is attributed to logical "0" and the other, to "1") that result from the antihysteresis effect.