▎ 摘　　要

In this paper, we investigate the graphene field effect transistor (G-FET) to enhance the drain current saturation and to minimize the drain conductance (gd) using numerical simulation. This work focus on suppressing the drain conductance using silicon substrate. We studied the impact of different substrate on the performance of band gap engineered G-FET device. We used a non-equilibrium green function with mode space (NEGF_MS) to model the transport behavior of carriers for 10 nm channel length G-FET device. We compared the drain current saturation of G-FET at higher drain voltage regime on silicon, SiC, and the SiO2 substrate. This paper clearly demonstrates the effect of substrate on an electric field near drain region of G-FET device. It is shown that the substrate of G-FET is not only creating a band gap in graphene, which is important for current saturation and gd minimization, but also selection of suitable substrate can suppress generation of carrier concentration near drain region is also important. (C) 2017 Elsevier Ltd. All rights reserved.