▎ 摘　　要

We demonstrate and explain the operation of a multi-level nonvolatile memory system using dual-gated single-layer graphene field-effect transistor with a polymer ferroelectric as top-gate dielectric and a linear bottom-gate dielectric. The multiple memory states are represented by various levels of graphene channel resistance obtained by changing the doping type and the number of p-n junctions in graphene. This is achieved by controlling the polarity of the domains in the ferroelectric thin film using a biased metal-coated atomic force microscope tip. We show a five level memory with the resistance change between the lowest and highest state greater than 200%. (C) 2013 AIP Publishing LLC.