▎ 摘　　要

In the present work, we report fabrication and electrical characterization of a back gated graphene field effect transistor (GFET). We have focused our study on the interfacial effect (graphene/SiO2) on the performance of the device. Hysteresis was observed in the drain conductance when measured with respect to dual gate sweep voltage, which increases with increasing sweeping voltage range. The conductance was observed to increase with increase in temperature but there was no reduction in the hysteresis. This proved that temperature annealing could improve the channel conductivity but not the interfacial effects. Further, a metal oxide semiconductor (MOS) device was fabricated with SLG inserted in between the metal and oxide layer and its capacitance-voltage (C-V) characteristics were studied. A small series capacitance (2.1 nF) was observed to be existing in series with the oxide capacitance (4.5 nF) which was attributed to the trap states at the interface of graphene and SiO2 layer. Also, the flat band voltage was not affected by the incorporation of graphene layer in the MOS device indicating no change in the work function of the metal gate (Cr/Au). This is an advantageous situation where graphene does not alter its work function also being impermeable, restricts the diffusion of metal particles through the SiO2.