▎ 摘　　要

We have explored the dielectrophoretic process (DEP) to reach large scale integration of field effect transistors based on multilayer graphene (GraFET) deposited between source and drain metal electrodes. In our devices graphene lays on top of a TaOx gate dielectric deposited on an n_silicon substrate, which is used as the back gate electrode, while the metal electrodes are made of TaN. These GraFETs reached a maximum transconductance of -19 mS/mm, which is higher than in silicon MOSFETs. To explain the origin of such good performance at the atomic level, ab initio calculations were conducted assuming two different models of the graphene/TaN interface: Ta- and N-terminated delta-TaN[111] surfaces with one, two, three, and four layers of graphene on top. We have found that all graphene layers are considerably deformed due to strong interaction with both metal surfaces, and remain non-planar up to the fourth layer. We have also found that, except for the first graphene layer on TaN, all other layers display the Dirac cones in their locally projected density of states (PDOS). The reason for the absence of the Dirac cones in the first layer, an indication of poor conductance for monolayer graphene on TaN, is the metal induced surface states and not graphene deformation. Finally, due to the large work function of N-terminated TaN, the first few graphene layers closest to the interface are strongly p-doped, while for the Ta-terminated TaN which has low work function the first few graphene layers are slightly n-doped. The better adherence of graphene on N-terminated TaN and the strong p-doping of the interfacial graphene layers may explain the measured low contact resistance. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim