• 文献标题:   Barrier engineering for double layer CVD graphene tunnel FETs
  • 文献类型:   Article
  • 作  者:   ROY T, HESABI ZR, JOINER CA, FUJIMOTO A, VOGEL EM
  • 作者关键词:   tunnel fet, graphene, barrier engineering
  • 出版物名称:   MICROELECTRONIC ENGINEERING
  • ISSN:   0167-9317 EI 1873-5568
  • 通讯作者地址:   Georgia Inst Technol
  • 被引频次:   7
  • DOI:   10.1016/j.mee.2013.02.090
  • 出版年:   2013

▎ 摘  要

Atomic layer deposited high-k dielectrics with sputtered TiOx as the seeding layer have been explored for double layer graphene tunnel transistors. The subthreshold swing of these transistors is <100 mV/decade. Temperature-dependent measurements indicate defect-mediated tunneling through these dielectrics. However, the current symmetry can still be altered by engineering the tunnel barriers. Published by Elsevier B.V.