• 文献标题:   Ultra-low power circuits using graphene p-n junctions and adiabatic computing
  • 文献类型:   Article
  • 作  者:   MIRYALA S, TENACE V, CALIMERA A, MACII E, PONCINO M
  • 作者关键词:   adiabatic circuit, graphene pn junction, low power circuit, graphene nanoelectronic
  • 出版物名称:   MICROPROCESSORS MICROSYSTEMS
  • ISSN:   0141-9331 EI 1872-9436
  • 通讯作者地址:   Politecn Torino
  • 被引频次:   3
  • DOI:   10.1016/j.micpro.2015.05.018
  • 出版年:   2015

▎ 摘  要

Recent works have proven the functionality of electrostatically controlled graphene p-n junctions that can serve as basic primitive for the implementation of a new class of compact graphene-based reconfigurable multiplexer logic gates. Those gates, referred as RG-MUXes, while having higher expressive power and better performance w.r.t. standard CMOS gates, they also have the drawback of being intrinsically less power/energy efficient. In this work we address this problem from a circuit perspective, namely, we revisit RG-MUXes as devices that can operate adiabatically and hence with ultra-low (ideally, almost zero) power consumption. More specifically, we show how to build basic logic gates and, eventually, more complex logic functions, by appropriately interconnecting graphene-based p-n junctions as to implement the adiabatic charging principle. We provide a comparison in terms of power and performance against both adiabatic CMOS and their non-adiabatic graphene-based counterparts; characterization results collected from SPICE simulations on a set of representative functions show that the proposed ultra-low power graphene circuits can operate with 1.5-4 orders of magnitude less average power w.r.t adiabatic CMOS and non-adiabatic graphene counterparts respectively. When it comes to performance, adiabatic graphene shows 1.3 (w.r.t. adiabatic CMOS) to 4.5 orders of magnitude (w.r.t. non-adiabatic technologies) better power-delay product. (C) 2015 Elsevier B.V. All rights reserved.