▎ 摘　　要

Here, we theoretically and experimentally investigate the impact of a high-kappa layer inserted between graphene and p-Si in a graphene/Si junction. We have achieved 86-fold and 222-fold reductions in a specific contact resistivity (rho(c)) by inserting 1-nm-thick Al2O3 and 2-nm-thick TiO2 in the graphene-semiconductor junction, respectively, corresponding to lowering the effective barrier height by 0.24 and 0.12 eV. Furthermore, we propose a graphene-induced gap state model that simultaneously considers the graphene's modulation by a gate bias and the effect of the high-kappa insertion.