▎ 摘　　要

In this paper, a resistance-based drain current model for dual-gate graphene FETs (GFETs) is presented, in which an existing analytical model for the sheet charge density for dual-gate structures has been extended for single-gate architectures. In addition, in order to ensure charge and potential continuity throughout the device, unaccounted for in the literature, a new parameter, Debye length, for graphene has been introduced, and a heuristic model for it has been proposed. The carrier mobility in graphene has been modeled in this paper by proposing a new hypothesis for carrier transport in the graphene layer of GFETs, and is a function only of the applied voltages-resulting in significant savings in terms of computational time. Also, the source and drain region resistances (assumed constant in the literature, which is physically unacceptable) have been modeled in this paper based on the charge distributions in these regions. The modeled drain current not only produced well-behaved drain conductance and transconductance over the entire bias range but also showed a very good match with the experimental data published elsewhere, while reducing the maximum error as compared with the simulated results of some existing works.