▎ 摘　　要

Investigations of the fundamental properties of graphene have leveraged the versatility of the CMOS fabrication platform early on by using oxidized semiconductor substrates with a highly doped back gate to behave as a metal gate down to cryogenic temperatures. For future applications at room temperature and co-integration with standard silicon circuits, standard substrates should be considered and modeled. Therefore, we investigate the impact of using standard lightly doped silicon as a back gate by building upon existing drift-diffusion models for the 3-terminal monolayer graphene field effect transistor. Typical measurements of the back-gate transfer characteristics exhibit a kink/plateau around 0 V. This effect is explained by the proposed model and corresponds to a loss of gate control occurring during the formation of the depletion layer in the substrate. The impact is increased at low temperature, for thin oxides or under transient conditions.