▎ 摘　　要

We report a method of fabricating self-aligned, top-gated graphene field-effect transistors (GFETs) employing polyethyleneimine spin-on-doped source/drain access regions, resulting in a 2X reduction of access resistance and a 2.5X improvement in device electrical characteristics, over undoped devices. The GFETs on Si/SiO2 substrates have high carrier mobilities of up to 6300 cm(2)/Vs. Self-aligned spin-on-doping is applicable to GFETs on arbitrary substrates, as demonstrated by a 3X enhancement in performance for GFETs on insulating quartz substrates, which are better suited for radio frequency applications. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4765658]