▎ 摘　　要

Brain-inspired or neuromorphic computing has been proposed as a method to overcome the limitations of the von-Neumann architecture. Neuromorphic computing relies on an array of neurons interconnected locally through synapses to perform computing functions such as pattern recognition and image processing. Neuromorphic computing with CMOS-based circuits has limited utility due to the relatively large area required by neurons and synapses, limiting the size of the neuromorphic network implementable on chip. In this paper, we present a novel ultracompact graphene variable resistor that can be used to implement both neurons and synapses. To illustrate the functionality of the proposed devices, we present a 3-bit digitally controlled synapse prototype that occupies 3 mu m x 9.3 mu m. The proposed devices pave the way for high-performance large neuromorphic networks that can be integrated with CMOS to augment its functionality or for beyond CMOS computation.