▎ 摘　　要

The combination of quantum Hall conductance and charge-trap memory operation was qualitatively examined using a graphene field-effect transistor. The characteristics of two-terminal quantum Hall conductance appeared clearly on the background of a huge conductance hysteresis during a gate-voltage sweep for a device using monolayer graphene as a channel, hexagonal boron-nitride flakes as a tunneling dielectric and defective silicon oxide as the charge storage node. Even though there was a giant shift of the charge neutrality point, the deviation of quantized resistance value at the state of filling factor 2 was less than 1.6% from half of the von Klitzing constant. At high Landau level indices, the behaviors of quantum conductance oscillation between the increasing and the decreasing electron densities were identical in spite of a huge memory window exceeding 100 V. Our results indicate that the two physical phenomena, two-terminal quantum Hall conductance and charge-trap memory operation, can be integrated into one device without affecting each other.