▎ 摘　　要

Graphene Nanoribbon (GNR) has shown to have great advantages over conventional Silicon for the next generation of CMOS. In this paper, graphene nanoribbon field-effect transistor (GNRFET) is analytically modeled. To test its flexibility, the developed GNRFET model is then implemented in SPICE to evaluate its circuit level performance for different various basic logic gates circuit utilizing the Copper (Cu), multiwalled carbon nanotube (MCNT) and GNR wire. At the gate length of 22 nm GNRFET, the circuit performance is benchmarked against 22 nm node MOSFET. The key parameter assesses includes energy delay product (EDP), power delay product (PDP) and propagation delay. GNRFET shown reduction in the EDP and PDP over 100 times and lowering in propagation delay of almost 80% compared to MOSFET. In addition, the used of GNR as interconnect wire can reduce the EDP and PDP as well as propagation delay in both GNRFET and MOSFET. Benchmarking analysis obtained suggest that GNRFET is likely to be one of the potential successor for high speed with low power and energy benefits.