▎ 摘　　要

Silicon-based electronics is going to face limitations and need to be replaced by alternative materials. Carbon is one of the most probable candidates. In every digital IC, Input/Output block is needed to interface the internal logic with the off-chip world and is a crucial for each IC. Toward all-carbon electronics, I/O block has to be redesigned and characterized. In this paper, an optimized and low-area graphene-based I/O block is proposed. A novel design algorithm is developed to size the graphene-based buffer chain, which is capable of driving a large off-chip load. Besides the buffer chain, required sub-circuits such as level-shifter, Schmitt-trigger, tristate buffer, flip-flop, and MUX are also designed to build a complete I/O block. Using effective modelling and intensive simulation, blocks designed, modelled, and characterized. Results indicate that graphene-based I/O block is feasible. The propagation delay is reduced by 5.2 times and occupied area reduced 2/3 compared with the silicon-based I/O block. The proposed I/O block can drive capacitive load as large as 50 pF, which is higher than the silicon-based I/O. Using GNR, a layout is presented for I/O block. It is shown that the proposed I/O block can communicate with an efficient speed while it has Nano-scale size.