• 专利标题:   Method for manufacturing independent dual-gate graphene FET, involves forming germanium silicide epitaxial layer on silicon substrate, implanting carbon ions into silicon substrate, followed by thermally annealing.
  • 专利号:   CN107437505-A, TW604535-B1, TW201810438-A
  • 发明人:   XIAO D
  • 专利权人:   ZING SEMICONDUCTOR CORP, ZING SEMICONDUCTOR CORP
  • 国际专利分类:   H01L021/02, H01L021/336, H01L029/16, H01L029/78
  • 专利详细信息:   CN107437505-A 05 Dec 2017 H01L-021/336 201802 Pages: 10 Chinese
  • 申请详细信息:   CN107437505-A CN10356807 26 May 2016
  • 优先权号:   CN10356807

▎ 摘  要

NOVELTY - An independent dual-gate graphene FET manufacturing method involves forming a germanium silicide epitaxial layer on a silicon substrate, implanting carbon ions into the silicon substrate, thermally annealing to synthesize silicon carbide precipitates directly, where the carbon lattice of the silicon is the same as the lattice of the germanium silicide, in the silicon carbide table, followed by selectively growing graphene, forming a dielectric layer on the graphene, patterning, and forming a source and a drain on the graphene and forming the gate on the dielectric layer. USE - Method for manufacturing independent dual-gate graphene FET. ADVANTAGE - The method enables manufacturing the independent dual-gate graphene FET with high hardness to avoid damage caused by transferring graphene, and high thermal conductivity, high electron mobility, low resistance and excellent characteristics, and achieves small size, high speed, low energy consumption and low heat-generating product performance. DETAILED DESCRIPTION - An independent dual-gate graphene FET manufacturing method involves forming a germanium silicide epitaxial layer on a silicon substrate, implanting carbon ions into the silicon substrate, thermally annealing to synthesize silicon carbide precipitates directly, where the carbon lattice of the silicon is the same as the lattice of the germanium silicide, in the silicon carbide table, followed by selectively growing graphene, forming a dielectric layer on the graphene, patterning, where the patterned pattern width is less than 10 nm, and forming a source and a drain on the graphene and forming the gate on the dielectric layer.