▎ 摘　　要

NOVELTY - The device (100) has a first source/drain region (103) and a second source/drain region (105) that are arranged in a semiconductor substrate (101). A word line structure (WL) is arranged in the semiconductor substrate and between the first source/drain region and the second source/drain region. The word line structure comprises a gate dielectric layer (113). A lower electrode layer (115) is arranged over the gate dielectric layer. An upper electrode layer (119) is arranged over the lower electrode layer. A first graphene layer (117,135,139) is arranged between the lower electrode layer and the upper electrode layer. A dielectric cap layer (123,141) is aranged over the word line structure, and the dielectric cap layer is in direct contact with the first graphene layer of the word line structure. USE - Semiconductor device such as dynamic random access memory (DRAM) and peripheral metal-oxide-semiconductor (MOS) transistor. ADVANTAGE - The graphene layer is configured to lower the resistance of the word line structure and/or the bit line structure, so that the operation speed of the semiconductor device can be increased, which significantly improves the overall device performance. The semiconductor devices are becoming smaller in size while providing greater functionality and including greater amounts of integrated circuitry with the advancement of electronic technology. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of the semiconductor device. Semiconductor device (100) Semiconductor substrate (101) First source/drain region (103) Second source/drain region (105) Gate dielectric layer (113) Lower eletrode layer (115) First graphene layers (117,135,139) Dielectric cap layers (123,141)