▎ 摘　　要

NOVELTY - The transistor (100) has a first source/drain pattern formed on a substrate (110). A second source/drain pattern is spaced apart from the first source/drain pattern in a first direction on the substrate. A first channel layer (121) and a second channel layer (122) are formed between the first source/drain pattern and the second source/drain pattern. A first graphene barrier is formed between the first channel layer and the first source/drain pattern. A gate insulating layer (140) surrounds the first channel layer. A gate electrode (160) surrounds the first channel layer with the gate insulating layer. The first graphene barrier extends to an area between the second channel layer and the first source/drain pattern, where the first graphene barrier includes nanocrystalline graphene. USE - Multi bridge channel field effect transistor (FET) for use in various integrated circuit (ICs) devices e.g. memories, driving ICs and logic devices. ADVANTAGE - The transistor improves current density and reduces size, while maintaining performance. The transistor forms graphene barrier by performing a chemical vapor deposition process or an atomic layer deposition process. The transistor reduces space in the integrated circuit device rapidly, so that the size of the transistor is reduced and channel length is reduced effectively. The transistor prevents threshold voltage variation, carrier velocity saturation and deterioration of sub threshold characteristics. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for manufacturing a multi bridge channel field effect transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a multi bridge channel field effect transistor. 100Multi bridge channel field effect transistor 110Substrate 121, 122Channel layers 140Gate insulating layer 160Gate electrode