• 专利标题:   Method for preparing graphene FET by using dielectric sacrificial layer process, involves using atomic layer deposition (ALD) process to grow high K gate dielectric, and completing metallization by evaporation, and preparing gate electrode.
  • 专利号:   CN113097072-A, CN113097072-B
  • 发明人:   CAO Z, WU Y, GU X, WEI Z
  • 专利权人:   55TH RES INST CHINA ELECTRONIC TECHNOLOG
  • 国际专利分类:   H01L021/336, H01L029/16, H01L029/78
  • 专利详细信息:   CN113097072-A 09 Jul 2021 H01L-021/336 202164 Pages: 6 Chinese
  • 申请详细信息:   CN113097072-A CN10230544 02 Mar 2021
  • 优先权号:   CN10230544

▎ 摘  要

NOVELTY - The method involves using chemical vapor deposition to grow graphene, evaporating a layer of metal on surface of graphene, and using metal transfer graphene process to transfer graphene to an insulating substrate. The isolation area pattern is prepared using planar photolithography and development technology, the metal outside the isolation area is removed by wet etching, and graphene outside isolation area is oxidized to remove the graphene outside the isolation area. A dry growth process is adopted, and a dielectric sacrificial layer is grown on the surface of substrate. The atomic layer deposition (ALD) process is used to grow the high-K gate dielectric, and the metallization is completed by evaporation, and the gate electrode is prepared by the sol stripping technology, and the preparation of the graphene FET is completed. The evaporated metal on the graphene surface is gold, copper, or palladium. The dielectric sacrificial layer is silicon oxide or silicon nitride. USE - Method for preparing graphene FET by using dielectric sacrificial layer process. ADVANTAGE - The method reduces the parasitic resistance. The dielectric sacrificial layer protects the graphene FET after the graphene FET is finished, which is equivalent to finishing passivation, which is good for application in the circuit flow sheet process. The method improves the graphene FET performance. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view illustrating the method for preparing graphene FET by using dielectric sacrificial layer process. (Drawing includes non-English language text)