▎ 摘　　要

NOVELTY - The method involves forming a graphene liner layer (26B) in a trench/via (14). A copper-based seed layer is formed on the graphene layer. Bulk copper-based material (20) is deposited on the copper- based layer to overfill the trench/via. A chemical mechanical polishing process is performed to remove excess amounts of bulk copper-based material and the copper-based layer positioned outside of the trench/via to define a copper-based conductive structure with the graphene liner layer positioned between the copper-based structure and a layer of insulating material (10) e.g. silicon dioxide. USE - Method for forming a graphene liner and a capping layer on a copper-based conductive structure i.e. conductive line or via, of an integrated circuit device e.g. application specific integrated circuit device (ASIC), logic device and memory device, for a technology e.g. C-metal-oxide-semiconductor technology, N-channel FET (NFET) and P-channel FET (PFET). Can also be used for a CPU and a storage device. ADVANTAGE - The method enables performing the chemical mechanical polishing process to remove excess amounts of the copper-based material and the copper-based seed layer positioned outside of the trench/via and forming the graphene liner and the capping layer on the copper-based conductive structure of the integrated circuit, thus enhancing performance of a semiconductor device and overall functionality of the integrated circuit in a cost-effective manner. DETAILED DESCRIPTION - The method enables forming a barrier liner layer above the layer of insulating material, where the barrier liner layer is made of tantalum, tantalum nitride and ruthenium. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a structure for forming graphene liners and capping layers on a copper-based conductive structure. Insulating material (10) Trench/via (14) Bulk copper-based material (20) Selective graphene deposition process (26) Graphene liner layer (26B)