• 专利标题:   Graphene Allylprodine Hall element integrated circuit, has circuit chip whose core circuit region is provided with multiple metal interconnection electrodes, and metal pressure welding area electrode covered with passivation layer.
  • 专利号:   CN103066098-A, CN103066098-B
  • 发明人:   PENG L, WANG S, ZHANG Z, XU H
  • 专利权人:   UNIV PEKING
  • 国际专利分类:   H01L023/538, H01L027/22, H01L043/06, H01L043/10, H01L043/14
  • 专利详细信息:   CN103066098-A 24 Apr 2013 H01L-027/22 201364 Pages: 12 Chinese
  • 申请详细信息:   CN103066098-A CN10575355 26 Dec 2012
  • 优先权号:   CN10575355

▎ 摘  要

NOVELTY - The circuit has a silicon-based complementary metal-oxide-semiconductor (CMOS) circuit chip whose core circuit region is provided with multiple metal interconnection electrodes. A metal pressure welding area electrode is covered with a passivation layer. A metal wire is electrically connected with an upper part of the passivation layer that is coated with an organic molecule layer, where the passivation layer is made of silicon nitride or aluminum oxide. USE - Graphene Allylprodine Hall element integrated circuit. ADVANTAGE - The circuit has high producing efficiency, and is inexpensive. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a graphene Allylprodine Hall element integrated circuit preparation method. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a graphene Allylprodine Hall element integrated circuit.