▎ 摘　　要

NOVELTY - The method involves depositing resist to pattern gate structure area over a graphene channel on a substrate (202). The gate dielectric and electrode materials are deposited over channel and resist. An anchor site formed of exposed portion of substrate is within channel. The resist and electrode and the dielectric materials are arranged above resist are lifted-off to form gate structure with gate electrode and dielectric spacer and to expose portions of channel that are adjacent to gate structure. The source and drain electrodes are formed over exposed portions of channel. USE - Method for fabricating graphene transistor device. ADVANTAGE - The resist and electrode and the dielectric materials are arranged above resist are lifted-off to form gate structure with gate electrode and dielectric spacer, so that the gate stack can be constructed with dielectric spacers permits the formation of an interface between a graphene layer and source and/or drain electrodes that is provided with consistent degree of contact and electrical conductivity. Thus, the good adhesion of the stack to the graphene and supporting substrate can be achieved. The parasitic resistances and capacitances can be minimized by the self-aligned gating so that the performance of the device for high-speed or high-frequency electronics can be enhanced. DESCRIPTION OF DRAWING(S) - The drawing shows a perspective view of the structure of graphene-based field-effect transistor (GFET) device. Substrate (202) Graphene layer (204) Structure of GFET device (400) Resist structure (402)