• 专利标题:   Integrated circuit structure for use in computer platform, has interconnect structure coupled to transistors, and graphene fixed over top surface of first metal, where first metal is copper, ruthenium cobalt and molybdenum or tungsten.
  • 专利号:   EP4109508-A2, US2022415818-A1, CN115527991-A, EP4109508-A3
  • 发明人:   NAYLOR C, CHAWLA J, METZ M, KING S, CHEBIAM R, KOBRINSKY M, CLENDENNING S, LEE S, JEZEWSKI C, CHUGH S, BIELEFELD J, CHU S, KIM S
  • 专利权人:   INTEL CORP, INTEL CORP, INTEL CORP
  • 国际专利分类:   H01L021/768, H01L023/532, H01L021/3215, H01L023/538
  • 专利详细信息:   EP4109508-A2 28 Dec 2022 H01L-021/768 202303 Pages: 23 English
  • 申请详细信息:   EP4109508-A2 EP178898 14 Jun 2022
  • 优先权号:   US358962

▎ 摘  要

NOVELTY - The structure has an interconnect structure coupled to transistors and comprising a first metal. A graphene is fixed over a top surface of the first metal, where an amount of a second metal, nitrogen or silicon within the structure is higher proximal to an interface of the graphene than distal from the interface. The first metal is copper, ruthenium, cobalt and molybdenum, or tungsten. The second metal is manganese, zinc, magnesium and cobalt, or aluminum. USE - Integrated circuit structure for use in a computer platform (claimed). ADVANTAGE - The method enables reducing resistance-capacitance (RC) delay associated with interconnects of an integrated circuit (IC) increases with density of the interconnect. The method allows the graphene to reduce electrical resistance of an interconnect structure, particularly a line. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are also included for: a computer platform; and a method for forming an integrated circuit interconnect structure. DESCRIPTION OF DRAWING(S) - The drawing shows a flow chart illustrating the method for forming an integrated circuit interconnect structure (Drawing includes non-English language text).