• 专利标题:   Double-line drain gate oxide layer graphene hetero-doped tunneling FET structure, has FET provided with source electrode and drain electrode, and double-gate connected with intrinsic graphene nano-meter belt and drain oxide layer.
  • 专利号:   CN104091829-A
  • 发明人:   GAO J, WANG W, ZHANG L, YUE G
  • 专利权人:   UNIV NANJING POST TELECOM
  • 国际专利分类:   H01L029/36, H01L029/49, H01L029/78
  • 专利详细信息:   CN104091829-A 08 Oct 2014 H01L-029/78 201502 Pages: 10 Chinese
  • 申请详细信息:   CN104091829-A CN10335055 14 Jul 2014
  • 优先权号:   CN10335055

▎ 摘  要

NOVELTY - The structure has a FET provided with a source electrode (S) and a drain electrode (D). A channel is connected with a source oxide layer (6), a drain oxide layer (7) and a double-gate (8). An end of the drain electrode is formed with a P-type heavy doping area (2) and connected with a graphene tunneling FET, a line-doped area (3), an intrinsic graphene nano-meter belt (1), a linear doped area (4) and an N-shaped heavily doped area (5). The double-gate is connected with the P-type heavy doped area, the line-doped area, the intrinsic graphene nano-meter belt and the drain oxide layer. USE - Double-line drain gate oxide layer graphene hetero-doped tunneling FET (DL-HTFET) structure. ADVANTAGE - The structure realizes shorter delay time and avoids DL-HTFET electric current leakages. DESCRIPTION OF DRAWING(S) - The drawing shows a front view of a double-line DL-HTFET structure. Drain electrode (D) Source electrode (S) Intrinsic graphene nano-meter belt (1) P-type heavy doping area (2) Line-doped area (3) Linear doped area (4) N-shaped heavily doped area (5) Source oxide layer (6) Drain oxide layer (7) Double-gate (8)