• 专利标题:   Interconnect structure comprises at least one opening in a dielectric layer, a graphene-based barrier metal layer disposed on dielectric layer, a seed layer, an electroplated copper layer, a planarized surface, and a capping layer.
  • 专利号:   US2013113102-A1, US9324634-B2
  • 发明人:   BAO J, YAO S, LI X, CHOI S S S
  • 专利权人:   INT BUSINESS MACHINES CORP, INT BUSINESS MACHINES CORP
  • 国际专利分类:   B82Y030/00, B82Y040/00, H01L021/768, H01L023/538, H01L023/48, H01L023/482, H01L023/532
  • 专利详细信息:   US2013113102-A1 09 May 2013 H01L-023/538 201332 Pages: 13 English
  • 申请详细信息:   US2013113102-A1 US291470 08 Nov 2011
  • 优先权号:   US291470

▎ 摘  要

NOVELTY - Interconnect structure comprises: at least one opening in a dielectric layer; a graphene-based barrier metal layer (106) disposed on the dielectric layer; a seed layer disposed on the graphene-based barrier metal layer; an electroplated copper layer disposed on the seed layer; a planarized surface, where a portion of the graphene-based barrier metal layer, the seed layer and the electroplated copper layer are removed; and a capping layer disposed on the planarized surface. USE - Used as interconnect structure. ADVANTAGE - The interconnect structure comprises a graphene-based barrier metal layer which blocks oxygen intrusion from a dielectric layer into the interconnect structure and blocks copper diffusion from the interconnect structure into the dielectric layer, thus improving integrated circuit performance, enhancing electromigration reliability of the interconnect structure, minimizing sudden data loss, and enhancing the useful lifetime of semiconductor integrated circuit products. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for fabricating the interconnect structure, comprising forming the opening in the dielectric layer, forming the graphene-based barrier metal layer disposed on dielectric layer, forming the seed layer on the graphene-based barrier metal layer, forming the electroplated copper layer on the seed layer, forming the planarized surface, and forming the capping layer disposed on the planarized surface. DESCRIPTION OF DRAWING(S) - The figure shows a cross-sectional view illustrating the formation of the trench areas and via holes having a barrier metal layer, a seed layer and an electroplated copper layer, where a dielectric capping layer is formed. Substrate (102) Transistor area layer (104) First dielectric layer (105) Barrier metal layer (106) First metal layer (107)