▎ 摘　　要

NOVELTY - The method involves providing (S1) a substrate. The silicon oxide layers are formed in the substrate. A graphene channel layer is formed (S2) on the silicon oxide layer. A source and a drain are formed (S3) at the two ends of the graphene channel layer. The silicon oxide layer between the source terminal and the drain terminal is removed (S4). A space is provided (S5) with a silicon oxide layer between the source end and the drain end of the graphene channel layer to form grid structure. USE - Manufacturing method of graphene FET (claimed). ADVANTAGE - The silicon oxide layers which contact with the graphene channel layer is reduced. The suspended graphene channel layer to be formed can be ensured. The pollution of the silicon oxide thin film to graphene can be reduced. The carrier mobility of the graphene channel layer between the source and the drain can be improved. The conductivity can be improved. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for graphene FET. DESCRIPTION OF DRAWING(S) - The drawing shows a flowchart illustrating the manufacturing process of graphene FET. (Drawing includes non-English language text) Step for providing substrate (S1) Step for forming graphene channel layer on silicon oxide layer (S2) Step for forming source and drain at two ends of graphene channel layer (S3) Step for removing silicon oxide layer between source terminal and drain terminal (S4) Step for providing space with silicon oxide layer (S5)