▎ 摘　　要

NOVELTY - High power density tunneling semiconductor device based on heterojunction comprises an axisymmetric structure including an N+ substrate. Pair of graphene source regions (3) arranged at intervals are arranged above the N-drift region. The N-drift region is provided with a gate dielectric layer partially overlapping with the graphene source region. A polysilicon gate is arranged on the gate dielectric layer, and a passivation layer is arranged on the polysilicon gate. The polysilicon gate and the source metal are spaced apart. A heterojunction is formed at the contact between the graphene source region and the N-drift region, and the graphene source region. A triple contact surface is formed between the drift region of the N-type region and the gate dielectric layer. The tunneling effect occurs at the triple interface. USE - Used as high power density tunneling semiconductor device based on heterojunction. ADVANTAGE - The device: has low requirement for injection process, small cell size, and large unit area cell number; improves the power density of the device; reduces the specific conduction resistor, and sub-threshold swing; simplifies the manufacturing process; reduces cost; improves the avalanche capability; and increases the breakdown voltage. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for manufacturing high power density tunneling semiconductor device based on heterojunction. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the high power density tunneling semiconductor device based on heterojunction (Drawing includes non-English language text). N + type silicon carbide substrate (1) N-type drift region (2.1) N-type drift region (2.2) Graphene source region (3) Forming source electrode metal (4) Partially overlapped gate dielectric layer (5) Polycrystalline silicon gate (6) Isolation passivation layer (7) Manufacturing drain electrode metal (8) P + type shielding layer (9)