• 专利标题:   Transistor e.g. junctionless field effect transistor has dielectric layer which is arranged on surface of active layer, dipole seed layer that is arranged on surface of dielectric layer away from active layer, and gate that is arranged on surface of dipole seed layer away from dielectric layer.
  • 专利号:   CN113130657-A, CN113130657-B
  • 发明人:   WANG X, ZHANG Z, TANG J, GAO B, WU H, QIAN H
  • 专利权人:   UNIV TSINGHUA
  • 国际专利分类:   H01L021/336, H01L029/49, H01L029/786
  • 专利详细信息:   CN113130657-A 16 Jul 2021 H01L-029/786 202170 Pages: 18 Chinese
  • 申请详细信息:   CN113130657-A CN11392800 30 Dec 2019
  • 优先权号:   CN11392800

▎ 摘  要

NOVELTY - The transistor has a dielectric layer (102) which is arranged on the surface of an active layer (101). A dipole seed layer (103) is arranged on the surface of the dielectric layer away from the active layer. A gate (104) is arranged on the surface of the dipole seed layer away from the dielectric layer. The material of the dielectric layer comprises a high-K material. The dipole seed layer comprises a two-dimensional material layer. The two-dimensional material of the two-dimensional material layer is selected from the molybdenum disulfide (MoS2), tungsten disulfide (WS2), tungsten diselenide (WSe2), molybdenum diselenide (MoSe2), graphene. The fermi level pinning is generated between the dipole seed layer and the gate. The effective work function of the transistor is increased by the first increment. USE - Transistor e.g. junctionless field effect transistor. ADVANTAGE - The junctionless field effect transistor provides effects of reducing leakage current, reducing static power consumption, and improving the stability of device performance. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method of making a transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a transistor. Active layer (101) Dielectric layer (102) Dipole seed layer (103) Gate (104) Channel region (1011)