▎ 摘　　要

NOVELTY - The method involves utilizing metal as gate medium mask for protecting a graphene top gate FET device. The graphene top gate FET device is etched. A gate-source is removed from the graphene top gate FET device. A gate drain in a graphene channel region is covered with a graphite material. The gate drain is plated with a metal layer. A gate-source is covered. A metal lead contact is formed. Distance between the gate-source and the gate drain is adjusted to reduce channel access resistance. USE - Method for reducing parasitic resistance of a graphene oxide top gate FET device. ADVANTAGE - The distance between the gate-source and the gate drain is adjusted to reduce the channel access resistance so as to effectively increase graphene top gate FET device current, transconductance and cutoff frequency. DETAILED DESCRIPTION - The graphene top gate FET device is formed with a gate dielectric layer made of silicon oxide, aluminum oxide, hafnium oxide, zirconium oxide or titanium oxide. The graphene top gate FET device is etched with etching solution of hydrofluoric acid, hydrochloric acid, phosphoric acid, sulfuric acid, nitric acid, potassium hydroxide solution or tetramethyl ammonium hydroxide. The metal layer comprises titanium and gold, nickel and gold, palladium and gold, chromium and gold or platinum and gold. DESCRIPTION OF DRAWING(S) - The drawing shows a cross sectional view of a graphene oxide top gate FET device.