▎ 摘　　要

NOVELTY - Completely and covalently linked whole reduced graphene oxide field effect transistor comprises silicon dioxide layer is loaded on the silicon wafer (Si) as a gate electrode, reduced graphene oxide (RGO) layers respectively connected as a source electrode and a drain electrode of a field-effect transistor (FET) on the fully reduced graphene oxide field effect transistor as the full covalent bond. The RGO layer is multiple pairs, and each pair of RGO layers is two, the two of the RGO layers are parallel to each other and loaded on the silicon dioxide layer, and a semi-RGO layer is loaded on the silicon dioxide layer around the RGO layer. The RGO layer functions as a semiconductor layer. USE - Used as completely and covalently linked whole reduced graphene oxide field effect transistor. ADVANTAGE - The transistor: can satisfy the requirement of providing real-time detection with low cost; is quick and simple; and provides a new idea for solution phase detection. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for preparing the covalently linked whole reduced graphene oxide field effect transistor comprising (a) treating the silicon wafer with silicon dioxide layer by using plasma for 5-25 minutes in an oxygen atmosphere, (b) firstly preparing the graphene oxide layer, then repeating the preparation of graphene oxide monolayer for 2-11 times on the silicon wafer to obtain graphene oxide layer comprising multiple graphene oxide monolayers on the silicon dioxide layer, (c) maintaining the silicon wafer at 180-500 degrees C for 8-15 hours under a reducing atmosphere to obtain silicon wafer loaded with RGO layer, (d) applying a mask to the silicon wafer loaded with RGO layer, depositing an aluminum film having a thickness of 20-90 nm, removing the mask after evaporating, performing plasma treatment in an oxygen atmosphere on the silicon wafers for 5-30 minutes for removing an RGO layer which is not covered by an aluminum film to obtain drain electrode and source electrode, soaking the silicon wafer in a dilute nitric acid aqueous solution at 30-100 degrees C for 30-60 minutes, taking out the silicon wafer and cleaning the surface of silicon wafer, (e) preparing again a graphene oxide layer for the second time, then repeating the preparation of the graphene oxide monolayer for 2-11 times on the silicon wafer to obtain graphene oxide layer comprising multiple graphene oxide monolayer on the silicon dioxide layer around the RGO layer, and (f) maintaining the silicon wafer obtained in the step (e) at 80-160 degrees C for 4-8 hours under an reducing atmosphere to obtain graphene oxide layer and semi-RGO layer, where the graphene oxide monolayer is prepared by immersing the silicon wafer in a silane coupling agent solution for 10-120 minutes, taking out the silicon wafer, cleaning for the first time, drying the surface of the first cleaned silicon wafer at room temperature, then placing the dried silicon wafer in a graphene oxide solution for 10-120 minutes, taking out and cleaning for the second time. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic representation of the completely and covalently linked whole reduced graphene oxide field effect transistor (Drawing includes non-English language text).