▎ 摘　　要

NOVELTY - The method involves arranging a gate medium layer on a T9-type gate metal electrode. A grid medium cover is arranged on a passivation protection layer. A side wall of the T-type gate metal electrode is arranged with the passivation protection layer. A foot cover of the T type gate metal electrode is removed by using the grid medium layer. Metal is coated on a source electrode and a drain electrode. A graphene top gate FET device body is connected with an electric conduction channel and the source and drain electrodes. The electric conduction channel is mounted on an insulation substrate. USE - Method for aligning graphene for top gate FET device. ADVANTAGE - The method enables ensuring simple graphene alignment process and reducing distance between a gate source and a gate drain so as to reduce parasitic gate path resistance value, thus improving performance level of a FET device. DETAILED DESCRIPTION - The T-type gate metal electrode is contained with etching gas. The etching gas is mixed with carbon fluoride gas, sulfur hexafluoride gas, hydrogen fluoride carbon gas and fluoroethylene carbon gas. The etching gas is nitrogen, oxygen, hydrogen, argon pneuma and helium. DESCRIPTION OF DRAWING(S) - The drawing shows a flow chart illustrating a method for aligning graphene for top gate FET device.'(Drawing includes non-English language text)'