▎ 摘　　要

NOVELTY - The transistor has an interlayer structure arranged between the source electrode and the drain electrode. A gate dielectric layer arranged between a middle portion of a channel and a side wall of an interlayer structure. A first insulating layer is attached to a lower surface of a gate. A second insulating sheet is attached on an upper surface of the gate. The gate is made of material graphene. The channel is provided with a first end and a second end that are respectively connected with a drain electrode and a source electrode. A middle portion is connected with the side walls of the interlayer structures. USE - Vertical transistor for use in integrated circuit. ADVANTAGE - The method enables reducing size of the vertical transistor in vertical and horizontal direction, and enhancing layout capability of the transistor, so that an integrated circuit can accommodate more transistors, allows the gate dielectric layer to be arranged between the middle part of the channel and the side wall of the interlayer structure so as to prevent the channel from being damaged. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for manufacturing of vertical transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the vertical transistor for use in integrated circuit. 3Grid 4Channel 11Connection part 12Vacant area