▎ 摘　　要

NOVELTY - The apparatus has a transistor i.e. back-gated FET (200), comprising a graphene layer (203) formed on a heavily doped substrate (201). Source/drain regions (204, 205) are spaced apart and relative to one another on the substrate, where the graphene layer comprises two portions. The portions are in contact with the respective source/drain regions, where cuts (230, 230-1, 230-2) are formed in the portions of the graphene layer to amplify transmission of carriers from the source/drain regions into the graphene layer. The cuts are formed perpendicular to the source/drain regions. USE - Integrated circuit apparatus for nanoelectronic applications. ADVANTAGE - The apparatus reduces contact resistance in graphene/metal contacts by forming the cuts in graphene in a contact region between the graphene and metal with high carrier mobility in an easy and cost-effective manner. The apparatus allows cut widths to remain as small as possible to avoid removing excessive amounts of the graphene in contact area. DESCRIPTION OF DRAWING(S) - The drawing shows an exploded perspective view of a FET. Back-gated FET (200) Heavily doped substrate (201) Graphene layer (203) Source/drain regions (204, 205) Cuts (230, 230-1, 230-2)