▎ 摘　　要

NOVELTY - The structure has a semiconductor layer including first region having doping concentration higher than doping concentration of peripheral region. A metal layer faces semiconductor; A graphene layer is between a semiconductor and metal layers; and a conductive metal oxide layer between a graphene and the semiconductor layers and covering a first region. The graphene layer includes nanocrystalline graphene (nc-G) or graphene sheet. The conductive layer includes two-component, three-component or four-component conductive layers. The insulating layer includes via hole through which first region is exposed, and metal silicide layer. USE - Interconnect structure for use in an electronic device (claimed) of DRAM memory. ADVANTAGE - The structure reduces contact resistance between layers and between wirings and devices, so that an operation delay of a device and an increase in power consumption can be reduced. The structure improves interlayer characteristics of the interconnect structure, thus improving reliability of the electronic device. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method for manufacturing an interconnect structure. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of an interconnect structure. Electronic device (800) Substrate (810) Interlayer insulating layer (820) Metal layer (840) Lower electrode (850)