• 专利标题:   Enhanced type graphene FET for integrated circuit, has main portion that is provided with gate region, source region, drain region, channel region and source/drain semiconductor doped region.
  • 专利号:   CN102593159-A
  • 发明人:   DU J, LIU J, SHI R
  • 专利权人:   UNIV SICHUAN
  • 国际专利分类:   H01L029/10, H01L029/78
  • 专利详细信息:   CN102593159-A 18 Jul 2012 H01L-029/10 201262 Pages: 8 Chinese
  • 申请详细信息:   CN102593159-A CN10072426 20 Mar 2012
  • 优先权号:   CN10072426

▎ 摘  要

NOVELTY - The FET has main portion that is provided with gate region, source region, drain region, channel region and source/drain semiconductor doped region. The dielectric material is composed of hafnium oxide (Hf02), hafnium silicate (HfSiO), nitrided hafnium silicates (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), alumina (A1203), lanthanum oxide (La203), zirconium oxide (Zr02), lanthanum aluminum oxide (LaAlO). The drain region is composed of aluminum, copper and metal material. USE - Enhanced type graphene FET for integrated circuit. ADVANTAGE - The component structure of the enhanced type graphene FET can be simplified. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the Enhanced type graphene FET.