▎ 摘　　要

NOVELTY - The forming method involves forming a FET (190), and a fuse (195) that includes a graphene layer (150) and electrically connected to the FET. The forming of fuse is comprised of forming the fuse in series with the FET and a fuse terminal on an end portion of the graphene layer. An isolation region (104) and well region (106) are formed in a substrate (102), and the source and drain regions (108a) are formed in the well region. A gate dielectric layer (111) is formed on the well region, and a gate electrode (110) is formed on the gate dielectric layer. USE - Forming method for semiconductor device, e.g. CMOS integrated circuits. ADVANTAGE - Ensures that the semiconductor device can be effectively blown by application of voltage to the graphene layer since the dimensions of the graphene layer can be sufficiently small. DESCRIPTION OF DRAWING(S) - The drawing shows a cross sectional view of a semiconductor device. Substrate (102) Isolation region (104) Well region (106) Source and drain regions (108a) Gate electrode (110) Gate dielectric layer (111) Graphene layer (150) FET (190) Fuse (195)